The present invention relates in general to integrated circuits, and in particular to an improved liquid-crystal display (LCD) column driver circuit that substantially reduces power consumption and size of the circuit.
A liquid-crystal display is made up of a liquid-crystal layer sandwiched between two layers of vertical and horizontal polarizers, and two layers of vertical and horizontal grid wires. An active matrix LCD panel has a built-in thin-film transistor at each (x,y) grid point. Each transistor is used to establish an analog voltage on its LCD grid point. An electrical capacitance at each grid point serves as a storage unit for the state of a cell and can hold the cell in that state until it is changed or refreshed by the transistor. That is, the cell capacitance storing the analog voltage enables a cell to remain on all the time and hence to be brighter than it would be if it had to be operated at a duty cycle below 100%. The crystals can also be dyed to provide color. The horizontal grid wires are sequentially driven by row driver circuits and connect to the control gates of all transistors in one row, enabling each cell in that row to be simultaneously updated with a new analog voltage (brightness). These analog voltages are supplied by a multitude of column drivers through the vertical grid wires.
Advantages of LCDs are low cost, low weight, small size and low power as compared to cathode ray tube (CRT) displays. These properties of LCDs allow them to be used in portable computers and miniature television sets with continuous-tone images. However, to generate grey tones (i.e., varying brightness) of the various colors, existing LCD driver circuits tend to consume a relatively large amount of power. This can be a major drawback in battery operated equipment such as portable computers.
Referring to FIG. 1, there is shown a block diagram of a typical LCD column driver circuit and an active matrix LCD. The LCD driver circuit receives digital image data serially at the serial input terminal 100. Each set of, for example, six (or more) serial bits of image data contain the brightness information for one color of one picture cell (or pixel) on the LCD panel. The data first undergoes a serial to parallel conversion. This is accomplished by feeding the data serially into a shift register 102, and once shift register 102 is filled, loading the data into a latch 104 in a parallel fashion. Each color of each pixel of data (e.g., six bits) is then applied to a digital to analog converter (DAC) 106. Assume for illustrative purposes that DAC 106 is a 6-bit DAC with an analog output voltage having 64 levels ranging from 0.1 volts to 6.4 volts with a 0.1 volt resolution. The analog output of each DAC 106 drives a column of pixels inside an active matrix LCD panel 108. Each pixel for each color includes a thin-film transistor 110 whose drain terminal connects to a column and gate terminal to a row of the display. The source terminal of transistor 110 connects to a storage capacitor 112 that stores the pixel value for the associated crystal. The storage capacitor may be the capacitance of the display itself.
A typical LCD panel may include for example 512 pixels across one row. For a color display, each pixel includes three display elements and transistors, one for red, one for green and one for blue. Thus, there may be a total of 1536 display elements per row in the display, each driven by its own DAC 106. The 1536 required DACs 106 may be divided into, for example, eight separate integrated circuit chips each having 192 DACs 106. Given the large number of DACs, the size and power consumption of each DAC 106 becomes critical.
FIGS. 2 and 3 show an example of a typical prior art implementation of a 6-bit DAC 106. A transformer 200 receives input voltages of, e.g., .+-.5 volts at the two inputs of its primary coil in an alternating fashion. The turns ratio of transformer 200 is designed such that 6.4 volts is equally divided into eight 0.8 volt increments provided at eight taps of the secondary coil. These coarse analog reference signals are supplied to the several multiple-DAC chips. Each multiple-DAC chip includes a global resistor divider chain 202 which includes eight equal value resistors (202i) connected between each pair of taps, for a total of 64 resistors 202i. Thus, the 0.8 volts between each pair of taps from the secondary coil is further divided into eight 0.1 volt intervals by resistor divider chain 202. The 64 fine analog reference voltage outputs from global resistor divider chain 202 are shared by the various DACs 106 on the chip (in the above example the chip includes 192 DACs 106). Each DAC 106 includes eight switch banks 204i of eight switches each that select one of the 64 analog reference voltages to be connected to the output of the DAC. Switches in switch banks 204i are controlled by decoders 206i that respond to the digital pixel data.
As shown in FIG. 3, each switch bank 204i is made up of eight switches 300. Each switch 300 is controlled by a six-input NAND gate 302 inside a decoder 206i. NAND gate 302 receives the six-bit pixel data from latch 104 (FIG. 1). Accordingly, the six-bit pixel data selects one of 64 discrete levels of analog voltages in 0.1 increments ranging from 0.1 to 6.4 volts to be supplied to the drain of the thin-film transistors in the active matrix LCD panel.
There are a number of drawbacks associated with the prior art circuit. First, according to this prior art implementation, each voltage output of global resistor divider chain 202 must be able to drive the large capacitive load associated with as many as 192 LCD columns. It is also possible that all bits driven by the DAC chip may be required to switch from, for example, 0.1 volts all the way to 6.0 volts at the same time. To accomplish this at an acceptable rate, the 6.0 volt tap on resistor divider 202-8 must exhibit very low impedance. This limits the maximum size of the resistors used in the global resistor divider chains 202. Employing relatively smaller resistance in the resistor dividers 202 results in larger current dissipation by each multiple-DAC chip. Given the large number of DACs 106 required in an LCD driver system, the total current dissipated by the resistor dividers can add up to a significant amount. There is waste associated with this design since all eight resistive dividers 202-1, 202-2, . . . 202-8 consume power even if only one, for example, the 6.0 volt tap in the 202-8 divider drives all DAC outputs. Further, the decoding scheme of the prior art requires a very large number gates (e.g., 64 6-input decoder gates) which adds to the circuit area.
There is therefore a need for an LCD column driver circuit that consumes less power and area.